This invention relates generally to static random-access-memory (SRAM), and more specifically to circuit improvements in such devices that allow faster operation and reduce the chance of unintentionally changing the states of stored data bits that are not desired to be changed.
By far the most widely used type of semiconductor memory is a dynamic random-access-memory (DRAM) because of its relatively low cost due to a high packing density of memory bit cells. However, DRAMs require a great deal of overhead circuitry, including circuits that periodically refresh the state of each of the bit cells. The SRAM requires no refreshing and generally has a faster access time, but suffers from the disadvantage that each bit cell is much larger than that of a DRAM. Therefore, a given semiconductor chip area of SRAM has significantly fewer number of storage cells than does an equal area of DRAM. But primarily because of the faster access time, SRAMs are used in many computer applications where that characteristic is important and thus the extra cost is justified. Many sophisticated general purpose computers use SRAM for a small part of its system memory, such as for a cache memory, and DRAM for the bulk of the memory.
A typical SRAM includes a separate memory cell circuit for each bit of information to be stored in the memory. Each bit cell circuit is in the nature of a flip-flop. It has two stable states. Its state is read by monitoring the voltage across it. If one side of the cell is high and the other is low, the bit cell is considered to be in one state, but if that voltage is reversed, it is considered to be in its second state. A cell's state is changed by applying an opposite voltage pulse across it.
SRAM arrays are organized with its bit cells in columns and rows. A plurality of such cells are arranged in a column with one side of each connected through a transistor switch to one column bit line and the other side of each connected through another transistor switch to a second column bit line. A number of such columns are utilized. A word control line is connected to the transistor switches of each cell in a row of cells extending across many columns. Proper energization of one word line thus connects the memory cells in one row to their respective column bit lines.
Reading the state of a cell in an array of cells is accomplished by a single reading circuit. Similarly, a single writing circuit is provided for an array of cells. A particular cell is addressed for reading or writing by properly energizing the word line in the row in which the cell exists, and by connecting the read or write circuits to the column bit lines in which the cell exists. The correct column bit lines are connected to the read or write circuits through an addressable decoding or multiplexing circuit. Under these conditions, only a single cell in the addressed column is connected to the column bit lines, that being the one in the row whose word line is addressed, and thus only that one cell is connected to the read or write circuits.
The reading circuit includes, as a primary component, a sense amplifier. Reading of an addressed cell is accomplished by connection of its column bit lines to the sense amplifier. The relative potential on the addressed column bit lines is measured to determine the state of the selected memory cell. If one bit line has a higher voltage than the other, then it is in one state, and if the voltages are reversed, then it is in the other state.
The state of an addressed cell is changed by addressing it in the same manner but then connecting the bit lines of the column in which the cell lies to the writing circuit. The writing circuit forces the cell to be switched in state by driving one of its bit lines high and simultaneously the other bit line low. When the writing circuit is disconnected from the addressed cell, the cell will stay in its new state until reversed by another writing process.
The usual SRAM circuit, when inactive, maintains all the bit lines at a voltage intermediate of the voltage difference across a memory cell. Thus, when a particular cell is addressed for reading its state, the bit lines to which it is connected begin at this intermediate voltage. This voltage is maintained by connection to a source through a reasonably high impedance, however, so that connection of the voltage difference across the cell to a pair of bit lines in a given column rapidly causes those voltages to change. It is this changing voltage in the bit lines of the addressed cell column that are sensed by the sense amplifier. The speed of the reading process is maximized by use of a very sensitive sense amplifier which can very early detect the direction of the voltage swing in the addressed column bit lines after the cell is connected to them by energizing the word line for the row of cells in which the addressed cell lies.
When writing a bit into an addressed cell by the write driving circuit being connected to the bit lines of an addressed column, the driving circuit rapidly changes the steady state equal voltages on the bit lines by raising one and lowering the other. After this, when the cell written to has been disconnected from its bit lines by its word line signal going inactive, the voltage on those bit lines is unequal, an undesirable condition in case some other cell in that column is next to be read. The memory must wait for those bit lines to come to an equal voltage before a reading operation of another cell in that column can be accomplished. The bit line voltages will be equalized in time because of their connection through a high impedance to a voltage source In order to speed up the process, however, all of the bit lines in the array or portion of array are pulsed, immediately after a single cell has been written, with a voltage to restore the bit lines of the column of the addressed cell to the desired equal level. The bit lines of each column are usually also connected together during this interval, the combination of events is designed to restore a pair of bit lines to an equal voltage condition so that a cell in that one column can be read.
This unequal bit line condition after a writing operation is also undesirable for another reason. If another cell in the column just written to is addressed too soon for reading, while the unequal bit line voltages are still far enough apart to be able to switch the state of a cell, that cell's state can be undesirably changed by the unequal voltage.
It is a primary object of the present invention to provide an SRAM from which stored data can be read with improved speed.
It is a more specific object of the present invention to provide an improved circuit technique for restoring to an equal voltage a pair of column bit lines which have just been driven unequal in the course of a writing operation.